Most important: AI chip test intensity and SoC TAM trajectoryIn the print: Semi Test segment revenue, AI revenue mix, memory test splitOn the call: HBM4 test complexity, SoC TAM 2026 outlook, compute vs networking mixDownstream: NVDA, TSMC, SK Hynix, MU, AVGO
House view
Street prices Teradyne as an AI test revenue growth story. We read this print primarily as a semiconductor test intensity signal, tracking whether AI chip production volumes at TSMC, SK Hynix, and Micron are accelerating fast enough to tighten automated test equipment capacity through 2026.
What is priced in
Street expects $1.19B revenue with 70%+ AI-driven mix, continuing the Q4 2025 surge. Not priced in: whether the SoC test total addressable market expansion Teradyne flagged (nearly 60% larger in 2025 vs 2024) is still accelerating or plateauing, which directly sizes the production ramp at TSMC N3/N2 for NVDA and custom accelerators. Also not priced in: whether HBM test intensity per stack is rising with HBM4 qualification, tightening test capacity for SK Hynix and Micron.
What to extract from this callRanked by constraint impact
Priority 1 · primary read
AI chip test intensity and SoC TAM trajectory
SoC test revenue is a direct proxy for advanced chip production volumes at TSMC and fabless designers like NVDA and AVGO. If the SoC TAM keeps expanding from its record 2025 level, it confirms accelerating wafer starts for AI accelerators and networking chips.
✓Semi Test segment revenue above $950M (vs $883M in Q4 2025) with AI mix at or above 70%, confirming TSMC N3/N2 production pull for NVDA and custom silicon is intensifying.
✗Semi Test segment below $883M or AI mix dropping below 65%, suggesting TSMC leading-edge utilization is flattening and NVDA/AVGO production cadence is decelerating.
Priority 2
HBM and DRAM test demand trajectory
Memory test revenue, 90% DRAM/HBM in 2025, directly tracks HBM production ramp at SK Hynix, Samsung, and Micron. Rising test intensity per HBM stack signals tightening production capacity for NVDA's supply chain.
✓Memory test revenue growing double-digits sequentially with DRAM/HBM share holding at 90%+, confirming HBM production scaling at SK Hynix and MU is pulling test capacity.
✗Memory test revenue flat or declining, or HBM share within memory shrinking, suggesting HBM yield improvements are reducing test time per stack and easing the equipment constraint.
Priority 3
Compute vs networking test mix within AI revenue
Working the eventRelease drop vs. Q&A
In the release · first 60 seconds
EPS (non-GAAP)
$2.08 consensus (Q1 2026); $1.80 prior quarter
Beat above $2.08 driven by Semi Test operating leverage confirms test demand intensity, not just mix.
Total revenue
$1.19B consensus; $1.08B prior quarter
Revenue above $1.19B with Semi Test as the primary driver confirms AI chip production pull is still accelerating.
Semi Test segment revenue
$883M (Q4 2025)
Above $950M confirms tightening test capacity for TSMC and memory makers. Below $883M signals deceleration.
AI revenue mix percentage
70%+ guided for Q1 2026; 60% in Q4 2025
At or above 70% confirms AI chip production intensity is broadening. Below 65% would flag a demand plateau.
Q2 2026 revenue guidance
No prior guide; Q1 consensus $1.19B
Sequential guide-up above $1.25B would confirm sustained equipment pull. Flat or down guide is the key risk.
Gross margin
57.5% (Q4 2025); 60.6% (Q1 2025)
Downstream readsOutcome → what it means for names we care about
Semi Test above $950M + AI mix at 70%+ + guide up
Test equipment constraint tightens for TSMC, SK Hynix, and MU. NVDA and AVGO chip production cadence is accelerating, confirming CoWoS and HBM capacity remain bottlenecks.
Semi Test above $950M + AI mix at 70%+ + flat guide
Current quarter confirms strong AI chip production at TSMC and memory makers, but flat guide suggests test demand may be peaking. NVDA supply constraint persists near-term but eases in H2.
Semi Test $883M-$950M + AI mix 65-70% + guide flat
AI chip production growth is decelerating from the Q4 2025 surge. TSMC leading-edge utilization is stabilizing, easing the test bottleneck for NVDA and AVGO ramps.
Semi Test below $883M + AI mix below 65% + guide down
Test demand is rolling over, suggesting TSMC and memory fab utilization is softening. NVDA and AVGO production schedules face less equipment friction but signal weaker end-demand.
227 signals · 2 high-qualityResearch read-through · not a trade recommendation
The split between compute and networking test reveals whether NVDA GPU production or custom ASIC/networking chip production (AVGO, MRVL) is the stronger pull. Q4 2025 was roughly 2/3 compute/networking and 1/3 memory.
✓Networking test growing faster than compute test, confirming AVGO and MRVL custom silicon ramps are adding a second vector of test demand beyond NVDA GPUs.
✗Networking test share shrinking within AI mix, suggesting custom ASIC ramps at AVGO and MRVL are slower than expected and NVDA GPU remains the sole driver.
Margin compression below 57% on higher revenue would suggest expedite costs from tight test capacity, confirming the constraint.
On the call · where the read moves
HBM4 test complexity vs HBM3E
Higher test time per HBM4 stack tightens test capacity at SK Hynix and MU, extending Magnum 7H demand into 2027.
SoC TAM 2026 sizing update
An upward revision from the record 2025 SoC TAM confirms TSMC N2 ramp is pulling more test hours per wafer for NVDA and AVGO.
Custom ASIC test demand from hyperscalers
Growing custom silicon test orders confirm AVGO and MRVL ASIC ramps are adding incremental test demand beyond NVDA GPUs.
Lead times and backlog commentary
Extending lead times confirm test equipment is capacity-constrained, limiting throughput for TSMC and memory fabs.
China exposure and export control impact
Reduced China test revenue frees capacity for leading-edge AI test, tightening allocation for SK Hynix and MU.